1. Technical Field of the Invention
The present invention relates to a solid-state imaging device, such as a CMOS image sensor, having an electronic shutter function, and to a control method for same.
2. Description of the Related Art
Conventionally, the CMOS image sensors mostly have electronic shutter functions. Differently from the CCD image sensors, because of the use of a focal plane shutter (rolling shutter) to reset the signals on a pixel-row basis by sequentially scanning a multiplicity of pixels arranged two-dimensional, there is a problem that exposure time deviates between the rows on the screen.
In this case, when shooting a vertically straight object moving in a horizontal direction, it comes out as if it were inclined.
FIG. 7A is an explanatory figure illustrating such a situation. After resetting the rows, the operation for transfer output (signal reading) is sequentially made on each row after a predetermined exposure time. As a consequence, the image obtained has a vertically straight object a moving sideways taken in an inclined state, as shown in FIG. 7C for example.
On the contrary, there exist those allowing shuttering on all the rows at the same time. In such a case, photodiodes (PDs) are reset simultaneously over all the rows at a certain point of time. After a predetermined exposure time, the charges on the PDs are transferred, simultaneously at all the rows, to a floating diffusion (FD). The FD signals are outputted row by row in the order.
FIG. 7B is an explanatory figure illustrating a situation like that. After resetting all the rows in batch, simultaneous transfer is done on all the rows, followed by an output on a row-by-row basis. By doing so, even in the case of shooting a vertical straight object a moving horizontally, it can be taken straight as it is as shown in FIG. 7D.
Meanwhile, there is a proposal having a transistor (drain Tr) capable of excluding PD extra charge directly onto the drain without passing through the FD, as a pixel circuit configuration for simultaneously resetting, with signal charge, the photodiodes (PDs) of all the pixels on a CMOS image sensor (see Patent Document 1).
[Patent Document 1]    JP-A-2001-238132
However, the CMOS image sensor in the all-the-pixel shutter scheme shown in FIG. 7B involves the following problems.
(1) In the duration of after a simultaneous transfer over all the rows and before a sequential output on a pixel-row basis, light might leak to the FD the amount of which is different between the rows to be outputted earlier and to be outputted later. This results in a worsened photographic image.
(2) Because the PDs are reset after outputting the information of all the rows, exposure is impossible in a duration from a simultaneous transfer over all the rows to a completion of outputting row by row the information of all the rows. This spends time uselessly. Meanwhile, because of difficulty in taking an exposure time period great, the sensitivity lowers where the subject is dark.
These problems are explained below in greater detail.
At first, as for the above (1), there is a difference of one frame-reading time between the row to be outputted at the head and the row to be outputted at the last, in respect of the time length from a transfer to an output. The amount of a leak light to the FD is nearly zero on the head row whereas the amount of a leak light on the last row amounts to one frame-reading time period.
Photoelectric conversion is effected also at the FD, to build up charges at the FD in an amount corresponding to that light amount. This charge is added to the signal charge transferred from the PD.
This results in, besides noise or shading, exceeding the amount of saturation signal to cause white skipping in the case of intense light. In this manner, the leak of light to the FD considerably worsens the photographic image.
In this relation, explanation is made with using FIGS. 8 and 9. FIG. 8 is a sectional view showing a structure of a photodiode peripheral part of the prior-art CCD solid-state imaging device.
The CCD solid-state imaging device has a photodiode (PD) 12, a reading channel part 14, a channel stop part 16, a vertical transfer register 18 and the like, formed in an upper layer region of a semiconductor substrate 10. A polysilicon transfer electrode 22 is arranged on an upper surface of the semiconductor substrate 10 through a gate insulation film 20, on which a shade film 26 is further arranged through an insulation film 24.
In the shade film 26, an opening 26A is formed corresponding to a light-receiving surface of the PD 12. Meanwhile, a planarizing film (upper-layered insulation film) 28 is formed on the shade film 26, on which a color filter 30 and micro-lens 32 is fitted.
In the CCD solid-state imaging device thus configured, the photoelectric charge on the PD 12 is read out simultaneously over the entire screen, and transferred to a vertical transfer register 18 through the reading channel part 14.
Thereafter, the photoelectric charge is conveyed row by row to an output amplifier (not shown) by the CCD of the vertical transfer register 18, then being outputted.
As shown in the figure, on the CCD solid-state imaging device, a metal layer of aluminum or the like to serve as a shade film 26 is formed extending down to an immediate vicinity of the PD 12, to prevent light from leaking to the vertical transfer register 18. Nevertheless, a slight part of light leaks to the vertical transfer register 18. This is responsible for the image deterioration in a vertical-line form, called smear.
FIG. 9 is a sectional view showing a construction of a photodiode peripheral part of the prior-art CMOS solid-state imaging device.
This CMOS solid-state imaging device has P-well regions 42, 44 as a device region formed in an upper-layered part of a semiconductor substrate (N-type silicon substrate) 40, to form a PD 46 and various gate elements in the P-well regions 42, 44. Note that, in the illustrated example, the P-well region 42 is formed therein with a PD 46, a transfer gate (MOS transistor) 48 and an FD 50 while the P-well region 44 is with a MOS transistor 52 of the peripheral circuit section.
Meanwhile, in the above of the semiconductor substrate 40, a polysilicon transfer electrode 56 of each gate is formed through a gate insulation film 54. In the upper layer than that, multi-level wiring layers 60, 62, 64 are formed through an interlayer insulation film 58. Of the multi-level wiring layers, the uppermost-layered film 64 is formed as a shade film.
Meanwhile, on the multi-level wiring layers, a color filter 72 and micro-lens 74 is arranged through a protection film (SiN) 70.
In this manner, in the CMOS solid-state imaging device, pixels are made by the use of a CMOS process similarly to the peripheral circuits, making it impossible to make a shade film (wiring layer 64) extending down to an immediate vicinity of the PD 46. Thus, it is impossible to fabricate a structure allowing light to enter only the PD 46.
Furthermore, because the metal wiring layer exists in plurality of layers, light is to be irregularly reflected upon the layers. For this reason, a great deal of light is to leak to the FD 50 as compared to the case of a CCD solid-state imaging device, as can be understood from FIG. 9.
Thus, the CMOS solid-state imaging device involves a problem that image deterioration is serious upon simultaneous transfer on all the rows.
Next, as for the above (2), resetting the PD is by draining the charge of the PD to the FD. At this time, in case the FD is in a signal holding state, the signal is to be destroyed. Consequently, PD resetting is possible only after all the rows of FD signal have been read out.
For this reason, there exists a CMOS sensor having a transistor (drain Tr) capable of draining PD extra charge directly to the drain without passage through the FD, as disclosed in the foregoing Patent Document 1. However, this still requires PD resetting via the FD. Unless the PD is reset after reading FD signals on all the rows, image deterioration results.
This is because of the following reason. Namely, because it is impossible to completely match the characteristics, such as threshold, between the transfer Tr for transferring PD charge to the FD and the drain Tr mentioned in the above. In case the PD is reset in the beginning of a storage time period by the drain Tr, the PD is not return to the reset state when transferring charge to the FD in the end of the storage time period by the transfer Tr. The difference might cause problems, such as fixed-pattern noise and afterimage, not to be removed by the later-processing circuit.
Accordingly, in order to obtain a preferred image, PD reset is not allowed before the FD signal has been read out on all the rows. Because no exposure time is available, sensitivity is lowered.
Furthermore, it has been revealed that, in case the PD is reset in a course of FD signal reading by the drain Tr, there encounters a delicate difference between the pixel status before and after resetting the PD thereby causing a problem that a horizontal line is seen in a relevant part of a photographic image.
Meanwhile, it has been also revealed that, in the presence of a drain Tr, there also encounters a problem that a dark current occurs at an oxide film interface in the beneath thereof which flows into the PD.
Therefore, it is an object of the present invention to provide a solid-state imaging device capable of relieving the restrictions on exposure time period, securing a sufficient exposure time period on swift operation, relatively reducing the noise amount due to light leak, and outputting a suitable image, in the case of realizing an entire-screen simultaneous shutter function by the use of a solid-state imaging device having such a device structure as the foregoing CMOS solid-state imaging device, and a controlling method for the same.